Physical Design Of Memory And Detection Of Stuck – At Faults

Fault detection in memories is an approach to practice fault analysis at the Transistor level of memory circuits by means of a specially designed fault injection block. This paper Proposed inject the single stuck-at fault at the nodes and observe the logic simulation of the block . This work introduces fault analysis capabilities to improve the skills in the field of memory testing. Test and diagnosis of memory circuits are therefore an important challenge for improving quality of next generation integrated circuits. During each memory write cycle , the current data is written into that address of the memory selected and during the read cycle the data is read from the selected memory location. Both the input and output are compared and fault is detected depending on the results. Keywords— SRAM cell, Memory array, Counter Controller, Decoder.